Struct stm32f103xx::can::RegisterBlock
[−]
[src]
#[repr(C)]pub struct RegisterBlock { pub can_mcr: CAN_MCR, pub can_msr: CAN_MSR, pub can_tsr: CAN_TSR, pub can_rf0r: CAN_RF0R, pub can_rf1r: CAN_RF1R, pub can_ier: CAN_IER, pub can_esr: CAN_ESR, pub can_btr: CAN_BTR, pub can_ti0r: CAN_TI0R, pub can_tdt0r: CAN_TDT0R, pub can_tdl0r: CAN_TDL0R, pub can_tdh0r: CAN_TDH0R, pub can_ti1r: CAN_TI1R, pub can_tdt1r: CAN_TDT1R, pub can_tdl1r: CAN_TDL1R, pub can_tdh1r: CAN_TDH1R, pub can_ti2r: CAN_TI2R, pub can_tdt2r: CAN_TDT2R, pub can_tdl2r: CAN_TDL2R, pub can_tdh2r: CAN_TDH2R, pub can_ri0r: CAN_RI0R, pub can_rdt0r: CAN_RDT0R, pub can_rdl0r: CAN_RDL0R, pub can_rdh0r: CAN_RDH0R, pub can_ri1r: CAN_RI1R, pub can_rdt1r: CAN_RDT1R, pub can_rdl1r: CAN_RDL1R, pub can_rdh1r: CAN_RDH1R, pub can_fmr: CAN_FMR, pub can_fm1r: CAN_FM1R, pub can_fs1r: CAN_FS1R, pub can_ffa1r: CAN_FFA1R, pub can_fa1r: CAN_FA1R, pub f0r1: F0R1, pub f0r2: F0R2, pub f1r1: F1R1, pub f1r2: F1R2, pub f2r1: F2R1, pub f2r2: F2R2, pub f3r1: F3R1, pub f3r2: F3R2, pub f4r1: F4R1, pub f4r2: F4R2, pub f5r1: F5R1, pub f5r2: F5R2, pub f6r1: F6R1, pub f6r2: F6R2, pub f7r1: F7R1, pub f7r2: F7R2, pub f8r1: F8R1, pub f8r2: F8R2, pub f9r1: F9R1, pub f9r2: F9R2, pub f10r1: F10R1, pub f10r2: F10R2, pub f11r1: F11R1, pub f11r2: F11R2, pub f12r1: F12R1, pub f12r2: F12R2, pub f13r1: F13R1, pub f13r2: F13R2, // some fields omitted }
Register block
Fields
can_mcr: CAN_MCR
0x00 - CAN_MCR
can_msr: CAN_MSR
0x04 - CAN_MSR
can_tsr: CAN_TSR
0x08 - CAN_TSR
can_rf0r: CAN_RF0R
0x0c - CAN_RF0R
can_rf1r: CAN_RF1R
0x10 - CAN_RF1R
can_ier: CAN_IER
0x14 - CAN_IER
can_esr: CAN_ESR
0x18 - CAN_ESR
can_btr: CAN_BTR
0x1c - CAN_BTR
can_ti0r: CAN_TI0R
0x180 - CAN_TI0R
can_tdt0r: CAN_TDT0R
0x184 - CAN_TDT0R
can_tdl0r: CAN_TDL0R
0x188 - CAN_TDL0R
can_tdh0r: CAN_TDH0R
0x18c - CAN_TDH0R
can_ti1r: CAN_TI1R
0x190 - CAN_TI1R
can_tdt1r: CAN_TDT1R
0x194 - CAN_TDT1R
can_tdl1r: CAN_TDL1R
0x198 - CAN_TDL1R
can_tdh1r: CAN_TDH1R
0x19c - CAN_TDH1R
can_ti2r: CAN_TI2R
0x1a0 - CAN_TI2R
can_tdt2r: CAN_TDT2R
0x1a4 - CAN_TDT2R
can_tdl2r: CAN_TDL2R
0x1a8 - CAN_TDL2R
can_tdh2r: CAN_TDH2R
0x1ac - CAN_TDH2R
can_ri0r: CAN_RI0R
0x1b0 - CAN_RI0R
can_rdt0r: CAN_RDT0R
0x1b4 - CAN_RDT0R
can_rdl0r: CAN_RDL0R
0x1b8 - CAN_RDL0R
can_rdh0r: CAN_RDH0R
0x1bc - CAN_RDH0R
can_ri1r: CAN_RI1R
0x1c0 - CAN_RI1R
can_rdt1r: CAN_RDT1R
0x1c4 - CAN_RDT1R
can_rdl1r: CAN_RDL1R
0x1c8 - CAN_RDL1R
can_rdh1r: CAN_RDH1R
0x1cc - CAN_RDH1R
can_fmr: CAN_FMR
0x200 - CAN_FMR
can_fm1r: CAN_FM1R
0x204 - CAN_FM1R
can_fs1r: CAN_FS1R
0x20c - CAN_FS1R
can_ffa1r: CAN_FFA1R
0x214 - CAN_FFA1R
can_fa1r: CAN_FA1R
0x21c - CAN_FA1R
f0r1: F0R1
0x240 - Filter bank 0 register 1
f0r2: F0R2
0x244 - Filter bank 0 register 2
f1r1: F1R1
0x248 - Filter bank 1 register 1
f1r2: F1R2
0x24c - Filter bank 1 register 2
f2r1: F2R1
0x250 - Filter bank 2 register 1
f2r2: F2R2
0x254 - Filter bank 2 register 2
f3r1: F3R1
0x258 - Filter bank 3 register 1
f3r2: F3R2
0x25c - Filter bank 3 register 2
f4r1: F4R1
0x260 - Filter bank 4 register 1
f4r2: F4R2
0x264 - Filter bank 4 register 2
f5r1: F5R1
0x268 - Filter bank 5 register 1
f5r2: F5R2
0x26c - Filter bank 5 register 2
f6r1: F6R1
0x270 - Filter bank 6 register 1
f6r2: F6R2
0x274 - Filter bank 6 register 2
f7r1: F7R1
0x278 - Filter bank 7 register 1
f7r2: F7R2
0x27c - Filter bank 7 register 2
f8r1: F8R1
0x280 - Filter bank 8 register 1
f8r2: F8R2
0x284 - Filter bank 8 register 2
f9r1: F9R1
0x288 - Filter bank 9 register 1
f9r2: F9R2
0x28c - Filter bank 9 register 2
f10r1: F10R1
0x290 - Filter bank 10 register 1
f10r2: F10R2
0x294 - Filter bank 10 register 2
f11r1: F11R1
0x298 - Filter bank 11 register 1
f11r2: F11R2
0x29c - Filter bank 11 register 2
f12r1: F12R1
0x2a0 - Filter bank 4 register 1
f12r2: F12R2
0x2a4 - Filter bank 12 register 2
f13r1: F13R1
0x2a8 - Filter bank 13 register 1
f13r2: F13R2
0x2ac - Filter bank 13 register 2