Struct cortex_m::peripheral::CBP

#[repr(C)]
pub struct CBP {
    pub iciallu: WO<u32>,
    pub icimvau: WO<u32>,
    pub dcimvac: WO<u32>,
    pub dcisw: WO<u32>,
    pub dccmvau: WO<u32>,
    pub dccmvac: WO<u32>,
    pub dccsw: WO<u32>,
    pub dccimvac: WO<u32>,
    pub dccisw: WO<u32>,
    pub bpiall: WO<u32>,
    // some fields omitted
}

Cache and branch predictor maintenance operations register block

Fields

iciallu: WO<u32>

I-cache invalidate all to PoU

icimvau: WO<u32>

I-cache invalidate by MVA to PoU

dcimvac: WO<u32>

D-cache invalidate by MVA to PoC

dcisw: WO<u32>

D-cache invalidate by set-way

dccmvau: WO<u32>

D-cache clean by MVA to PoU

dccmvac: WO<u32>

D-cache clean by MVA to PoC

dccsw: WO<u32>

D-cache clean by set-way

dccimvac: WO<u32>

D-cache clean and invalidate by MVA to PoC

dccisw: WO<u32>

D-cache clean and invalidate by set-way

bpiall: WO<u32>

Branch predictor invalidate all

Methods

impl CBP

pub fn iciallu(&self)

I-cache invalidate all to PoU

pub fn icimvau(&self, mva: u32)

I-cache invalidate by MVA to PoU

pub fn dcimvac(&self, mva: u32)

D-cache invalidate by MVA to PoC

pub fn dcisw(&self, set: u16, way: u16)

D-cache invalidate by set-way

set is masked to be between 0 and 3, and way between 0 and 511.

pub fn dccmvau(&self, mva: u32)

D-cache clean by MVA to PoU

pub fn dccmvac(&self, mva: u32)

D-cache clean by MVA to PoC

pub fn dccsw(&self, set: u16, way: u16)

D-cache clean by set-way

set is masked to be between 0 and 3, and way between 0 and 511.

pub fn dccimvac(&self, mva: u32)

D-cache clean and invalidate by MVA to PoC

pub fn dccisw(&self, set: u16, way: u16)

D-cache clean and invalidate by set-way

set is masked to be between 0 and 3, and way between 0 and 511.

pub fn bpiall(&self)

Branch predictor invalidate all