Struct cortex_m::peripheral::SCB [] [src]

#[repr(C)]
pub struct SCB { pub icsr: RW<u32>, pub vtor: RW<u32>, pub aircr: RW<u32>, pub scr: RW<u32>, pub ccr: RW<u32>, pub shpr: [RW<u8>; 12], pub shpcrs: RW<u32>, pub cfsr: RW<u32>, pub hfsr: RW<u32>, pub dfsr: RW<u32>, pub mmar: RW<u32>, pub bfar: RW<u32>, pub afsr: RW<u32>, pub cpacr: RW<u32>, // some fields omitted }

SCB register block

Fields

Interrupt Control and State

Vector Table Offset

Application Interrupt and Reset Control

System Control

Configuration and Control

System Handler Priority

System Handler Control and State

Configurable Fault Status

HardFault Status

Debug Fault Status

MemManage Fault Address

BusFault Address

Auxiliary Fault Status

Coprocessor Access Control

Methods

impl SCB
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Enables I-Cache if currently disabled

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Disables I-Cache if currently enabled

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Returns whether the I-Cache is currently enabled

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Invalidates I-Cache

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Enables D-cache if currently disabled

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Disables D-cache if currently enabled

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Returns whether the D-Cache is currently enabled

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Cleans D-cache

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Cleans and invalidates D-cache

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Invalidates D-cache by address

addr: the address to invalidate size: size of the memory block, in number of bytes

Invalidates cache starting from the lowest 32-byte aligned address represented by addr, in blocks of 32 bytes until at least size bytes have been invalidated.

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Cleans D-cache by address

addr: the address to clean size: size of the memory block, in number of bytes

Cleans cache starting from the lowest 32-byte aligned address represented by addr, in blocks of 32 bytes until at least size bytes have been cleaned.

[src]

Cleans and invalidates D-cache by address

addr: the address to clean and invalidate size: size of the memory block, in number of bytes

Cleans and invalidates cache starting from the lowest 32-byte aligned address represented by addr, in blocks of 32 bytes until at least size bytes have been cleaned and invalidated.