Struct cortex_m::peripheral::CPUID

#[repr(C)]
pub struct CPUID {
    pub base: RO<u32>,
    pub pfr: [RO<u32>; 2],
    pub dfr: RO<u32>,
    pub afr: RO<u32>,
    pub mmfr: [RO<u32>; 4],
    pub isar: [RO<u32>; 5],
    pub clidr: RO<u32>,
    pub ctr: RO<u32>,
    pub ccsidr: RO<u32>,
    pub csselr: RW<u32>,
    // some fields omitted
}

CPUID register block

Fields

base: RO<u32>

CPUID base

pfr: [RO<u32>; 2]

Processor Feature

dfr: RO<u32>

Debug Feature

afr: RO<u32>

Auxiliary Feature

mmfr: [RO<u32>; 4]

Memory Model Feature

isar: [RO<u32>; 5]

Instruction Set Attribute

clidr: RO<u32>

Cache Level ID

ctr: RO<u32>

Cache Type

ccsidr: RO<u32>

Cache Size ID

csselr: RW<u32>

Cache Size Selection

Methods

impl CPUID

pub fn select_cache(&self, level: u8, ind: CsselrCacheType)

Selects the current CCSIDR

• level: the required cache level minus 1, e.g. 0 for L1, 1 for L2
• ind: select instruction cache or data/unified cache

level is masked to be between 0 and 7.

pub fn cache_num_sets_ways(&self, level: u8, ind: CsselrCacheType) -> (u16, u16)

Returns the number of sets and ways in the selected cache